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144 pin SO-DIMM SDRAM Modules
HYS64V8200GDL HYS64V16220GDL
64MB & 128 MB PC100 / PC133
*
144 Pin Eight Byte Small Outline Dual-In-Line Synchronous DRAM Modules for PC 100 and PC133 notebook applications one bank 8M x 64 and two bank 16M x 64 non-parity module organisation Performance:
-7 PC133 2-2-2 fCK tAC Clock frequency (max.) Clock access time 133 5.4 -7.5 PC133 3-3-3 133 5.4 -8 PC100 2-2-2 100 6 Units MHz ns
* *
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Single +3.3V( 0.3V ) power supply Programmable CAS Latency, Burst Length and Wrap Sequence (Sequential & Interleave) Auto Refresh (CBR) and Self Refresh Decoupling capacitors mounted on substrate All inputs, outputs are LVTTL compatible Serial Presence Detect with E2PROM Uses 8M x 16 128Mbit SDRAM components 4096 refresh cycles every 64 ms Gold contact pad, JEDEC MO-190 outline dimensions This module family is fully compliant with the latest INTEL SO-DIMM layout and electrical specification All PC133 modules are fully backward compatible for PC100 applications.
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HYS64V8200GDL/HYS64V16220GDL 144 pin SO-DIMM SDRAM Modules
These INFINEON modules are industry standard 144 pin 8-byte Synchronous DRAM (SDRAM) Small Outline Dual In-line Memory Modules (SO-DIMM) which are organised as 8Mx64 (64MByte) and 16x64 (128MByte) high speed memory arrays designed for use in non-parity applications. These SO-DIMMs use SDRAMs in TSOPII packages. Decoupling capacitors are mounted on the board. The DIMMs use serial presence detects implemented via a serial E2PROM using the two pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All INFINEON 144-pin SO-DIMMs provide a high performance, flexible 8-byte interface in a 67,6 mm long footprint.
Product Spectrum:
Organisation 8M x 64 Partnumber HYS64V8200GDL-7 HYS64V8200GDL-7.5 HYS64V8200GDL-8 HYS64V16220GDL-7 HYS64V16220GDL-7.5 HYS64V16220GDL-8 Speed PC133-222 PC133-333 PC100-222 PC133-222 PC133-333 PC100-222 SDRAMs used 4 8Mx16 4k 12 8 8Mx16 BA0, BA1 9 64ms Row Addr. Bank Select Column Refresh Addr. Period
16M x 64
Note: All partnumbers end with a place code (not shown), designating the die revision. Consult factory for current
revision. Example: HYS64V16220GDL-8-C2, indicating Rev.C2 dies are used for SDRAM components.
Card Dimensions:
Organisation 8M x 64 16M x 64 Partnumber HYS64V8200GDL HYS64V16220GDL PCB-Board Layout INTEL Rev. 1.0/1.2 INTEL Rev. 1.0/1.2 L x H x T [mm] 67.60 x 25.40 x 3.80 67.60 x 31.75 x 3.80
Pin Names
A0-A11 BA0,BA1 DQ0 - DQ63 RAS CAS WE CKE0, CKE1 *) CLK0, CLK1 Address Inputs Bank Selects Data Input/Output Row Address Strobe Column Address Strobe Read / Write Input Clock Enable Clock Input DQMB0 - DQMB7 CS0, CS1 *) Vcc Vss SCL SDA N.C. Data Mask Chip Select Power (+3.3 Volt) Ground Clock for Presence Detect Serial Data Out for Presence Detect No Connection
*) CS1 and CKE1 on two bank modules only
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HYS64V8200GDL/HYS64V16220GDL 144 pin SO-DIMM SDRAM Modules
Pin Configuration
PIN # Front Side VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 Vss DQMB0 DQMB1 Vcc A0 A1 A2 Vss DQ8 DQ9 DQ10 DQ11 Vcc DQ12 DQ13 DQ14 DQ15 Vss NC NC CLK0 Vcc RAS WE CS0 CS1 PIN # Back Side VSS DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 Vss DQMB4 DQMB5 Vcc A3 A4 A5 Vss DQ40 DQ41 DQ42 DQ43 Vcc DQ44 DQ45 DQ46 DQ47 Vss NC NC CKE0 Vcc CAS CKE1 N.C.(A12) N.C.(A13) PIN # Front Side NC Vss NC NC Vcc DQ16 DQ17 DQ18 DQ19 Vss DQ20 DQ21 DQ22 DQ23 Vcc A6 A8 Vss A9 A10 Vcc DQMB2 DQMB3 Vss DQ24 DQ25 DQ26 DQ27 Vcc DQ28 DQ29 DQ30 DQ31 Vss SDA Vcc PIN # Back Side CLK1 Vss NC NC Vcc DQ48 DQ49 DQ50 DQ51 Vss DQ52 DQ53 DQ54 DQ55 Vcc A7 BA0 Vss BA1 A11 Vcc DQMB6 DQMB7 Vss DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 Vss SCL Vcc
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143
74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144
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HYS64V8200GDL/HYS64V16220GDL 144 pin SO-DIMM SDRAM Modules
WE CS0 DQMB0 DQ0-DQ7 DQMB1 DQ8-DQ15 CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D0 DQMB4 DQ32-DQ39 DQMB5 DQ40-DQ47 CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D2
DQMB2 DQ16-DQ23 DQMB3 DQ24-DQ31
CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D1
DQMB6 DQ48-DQ55 DQMB7 DQ56-DQ63
CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D3
A0-A11, BA0, BA1
D0-D3 D0-D3 E2PROM (256 word x 8 Bit) SA0 SA1 SA2 SCL SDA
VCC C 1-C 4 VSS
RAS CAS CKE0 CLK0 CLK1
D0-D3 D0-D3 D0-D3 D0-D3 4 SDRAM
Note: All resistors are 10 10 pF
SPB04133
Block Diagram for one bank 8M x 64 SDRAM DIMM - Module
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HYS64V8200GDL/HYS64V16220GDL 144 pin SO-DIMM SDRAM Modules
WE CS0 CS1 DQMB0 DQ0-DQ7 DQMB1 DQ8-DQ15 CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D0 CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D4 DQMB4 DQ32-DQ39 DQMB5 DQ40-DQ47 CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D2 CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D6
DQMB2 DQ16-DQ23 DQMB3 DQ24-DQ31
CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D1
CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D5
DQMB6 DQ48-DQ55 DQMB7 DQ56-DQ63
CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D3
CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D7
A0-A11, BA0, BA1 VC C C VSS RAS CAS CKE0 CKE1 CLK0 CLK1
D0-D7 D0-D7 D0-D7 D0-D7 D0-D7 D0-D3 D4-D7 4 SDRAM 4 SDRAM Note: All resistors are 10 E 2 PROM (256 word x 8 Bit) SA0 SA1 SA2 SCL SDA
Block Diagram for two bank 16M x 64 SDRAM DIMM - Module
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Absolute Maximum Ratings
Parameter Symbol min. Input / Output voltage relative to VSS Power supply voltage on VDD Storage temperature range Power dissipation (per SDRAM component) Data out current (short circuit) VIN, VOUT VDD T STG PD IOS - 1.0 - 1.0 -55 - - Limit Values max. 4.6 4.6 +150 1 50 V V
oC
Unit
W mA
Permanent device damage may occur if "Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to recommended operation conditions. Exposure to higher than recommended voltage for extended periods of time affect device reliability
DC Characteristics TA = 0 to 70 C; VSS = 0 V; VDD = 3.3 V 0.3 V
Parameter Symbol Limit Values min. Input high voltage Input low voltage Output high voltage (IOUT = - 4.0 mA) Output low voltage (IOUT = 4.0 mA) Input leakage current, any input (0 V < VIN < 3.6 V, all other inputs = 0 V) Output leakage current (DQ is disabled, 0 V < VOUT < VDD) VIH VIL VOH VOL II(L) IO(L) 2.0 - 0.5 2.4 - - 20 - 20 max. Vcc+0.3 0.8 - 0.4 20 20 V V V V A A Unit
Capacitance TA = 0 to 70 C; VDD = 3.3 V 0.3 V, f = 1 MHz
Parameter Symbol Limit Values 8M x 64 max. Input capacitance (A0 to A11, BA0, BA1) Input capacitance (RAS, CAS, WE, CKE0) Input Capacitance (CLK0, CLK1) Input capacitance (CS0) Input capacitance (DQMB0-DQMB7) Input / Output capacitance (DQ0-DQ63) Input Capacitance (SCL,SA0-2) Input/Output Capacitance CI1 CI2 CI3 CI4 CI5 CIO Csc Csd 28 25 35 25 10 12 8 0 16M x 64 max. 52 46 35 30 15 18 8 10 pF pF pF pF pF pF pF pF Unit
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Operating Currents per memory bank (TA = 0 to 70oC, VDD = 3.3V 0.3V)
(Recommended Operating Conditions unless otherwise noted)
Parameter & Test Condition
OPERATING CURRENT trc=trcmin., tck=tckmin. Ouputs open, Burst Length = 4, CL=3 All banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access PRECHARGE STANDBY CURRENT in Power Down Mode CS =VIH (min.), CKE<=Vil(max) PRECHARGE STANDBY CURRENT in Non-Power Down Mode CS = VIH (min.), CKE>=Vih(min) NO OPERATING CURRENT tck = min., CS = VIH(min), active state ( max. 4 banks) BURST OPERATING CURRENT tck = min., Read command cycling AUTO REFRESH CURRENT tck = min., Auto Refresh command cycling SELF REFRESH CURRENT Self Refresh Mode, CKE=0.2V tck = min. tck = Infinity tck = min. tck = Infinity CKE>=VIH(min.) CKE<=VIL(max.)
Symb.
-7/-7.5
-8
Note
ICC1
600
560
mA mA mA mA mA mA mA mA mA
1
ICC2P ICC2PS ICC2N ICC2NS ICC3N ICC3P
6 4 160 20 200 40
6 4 140 20 180 40
1 1
1
1 1 1
ICC4
600
560
mA mA
1,2
1
ICC5 ICC6
720 3.2
680 3.2 mA 1
Notes:
1. These parameters depend on the cycle rate. These values are measured at 133 MHz for-7/ -7.5 and 100 MHz for -8 modules. Input signals are changed once during tck, excepts for ICC6 and for standby currents when tck=infinity. 2. These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3 and BL=4 is assumed and the data-out current is excluded.
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HYS64V8200GDL/HYS64V16220GDL 144 pin SO-DIMM SDRAM Modules
AC Characteristics 1)2) TA = 0 to 70 C; VSS = 0 V; VDD = 3.3 V 0.3 V, tT = 1 ns Parameter
Symbol
Limit Values -7 PC133-222
min. max.
Unit
-7.5 PC133-333
min. max.
-8 PC100-222
min. max.
Clock and Access Time Clock Cycle Time CAS Latency = 3 tCK CAS Latency = 2 Clock Frequency CAS Latency = 3 tCK CAS Latency = 2 Access Time from Clock CAS Latency = 3 tAC CAS Latency = 2 Clock High Pulse Width Clock Low Pulse Width Transition time Setup and Hold Parameters Input Setup Time Input Hold Time Power Down Mode Entry time Mode Register Set-up time Common Parameters Row to Column Delay Time Row Precharge Time Row Active Time Row Cycle Time - - - - 2.5 2.5 0.3 133 133 5.4 5.4 - - 1.2 - - - - 2.5 2.5 0.3 133 100 5.4 6 - - 1.2 - - - - 3 3 0.5 100 100 6 6 - - 2 MHz MHz ns ns ns ns ns
2, 3
7.5 7.5
- -
7.5 10
- -
10 10
- -
ns ns
tCH tCL tT
tIS tIH tSB tRSC
1.5 0.8 - 1 2
- - 1 - -
1.5 0.8 - 1 2
- - 1 - -
2 1 - 1 2
- - 1 - -
ns ns
4 4
CLK 4 CLK 4 CLK
Power Down Mode Exit Setup Time tPDE
tRCD tRP tRAS tRC
15 15 42 60 14 1
- -
100k
20 20 45 67 15 1
- -
100k
20 20 50 70 16 1
- -
100k
ns ns ns ns ns CLK
5 5 5 5 5
- - -
- - -
- - -
Activate(a) to Activate(b) Command tRRD period CAS(a) to CAS(b) Command period tCCD
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Parameter
Symbol
Limit Values -7 PC133-222
min. max.
Unit
-7.5 PC133-333
min. max.
-8 PC100-222
min. max.
Refresh Cycle Refresh Period (4096 cycles) Self Refresh Exit Time Read Cycle Data Out Hold Time
Data Out to Low Impedance Time Data Out to High Impedance Time DQM Data Out Disable Latency
tREF tSREX
- 1
64 -
- 1
64 -
- 1
64 -
ms CLK 6
tOH tLZ tHZ tDQZ
3 0 3 -
- - 7 2
3 0 3 -
- - 7 2
3 0 3 -
- - 8 2
ns ns ns CLK
7
Write Cycle Data Input to Precharge (write recovery) DQM Write Mask Latency
tWR tDQW
2 0
- -
2 0
- -
2 0
- -
CLK CLK
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HYS64V8200GDL/HYS64V16220GDL 144 pin SO-DIMM SDRAM Modules
Notes: 1. All AC characteristics shown are for SDRAM components. An initial pause of 100s is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 2. AC timing tests have Vil = 0.4 V and Vih = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between Vih and Vil. All AC measurements assume tT =1ns with the AC output load circuit shownSpecified tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0 V ..
t CH CLOCK 1.4 V t CL t IH tT 2.4 V 0.4 V
t IS
INPUT tAC t LZ OUTPUT
1.4 V tAC t OH
I/O
1.4 V t HZ
IO.vsd
50 pF
Measurement conditions for tac and toh
3. If clock rising time is longer than 1ns, a time (tT -0.5) ns has to be added to this parameter. 4. If tT is longer than 1ns, a time (tT -1) ns has to be added to this parameter. 5. Any time that the refresh Period has been exceeded, a minimum of two Auto (CRB) Refresh commands must be given to "wake-up" the device. 6. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 7. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels.
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HYS64V8200GDL/HYS64V16220GDL 144 pin SO-DIMM SDRAM Modules
Serial Presence Detects A serial presence detect storage device - E2PROM - is assembled onto the module. Information about the module configuration, speed, etc. is written into the E 2PROM device during module production using a serial presence detect protocol ( I2C synchronous 2-wire bus) SPD-Table:
Byte# Description SPD Entry Value HEX 8M x 64 16M x 64 -7 -7.5 -8 -7 -7.5 -8 80 08 04 0C 09 01 02 40 00 01 75 75 A0 75 75 A0 54 54 60 54 54 60 00 80 10 00 01 0F 04 06 01 01 00 0E 75 54 00 00 0F A0 60 FF FF 14 A0 60 FF FF 14 75 54 00 00 0F A0 60 FF FF 14 A0 60 FF FF 14
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont'd) Module Interface Levels SDRAM Cycle Time at CL=3 SDRAM Access time from Clock at CL=3 Dimm Config (Error Det/Corr.) Refresh Rate/Type SDRAM width, Primary Error Checking SDRAM data width Minimum clock delay for back-to-back random column address Burst Length supported Number of SDRAM banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM module attributes SDRAM Device Attributes :General SDRAM Cycle Time at CL = 2 SDRAM Access Time from Clock at CL=2 SDRAM Cycle Time at CL = 1 SDRAM Access Time from Clock at CL=1 Minimum Row Precharge Time
128 256 SDRAM 12 9 1/2 64 0 LVTTL 7.5 / 10.0 ns 5.4 / 6.0 ns none Self-Refresh, 15.6s n/a tccd = 1 CLK 1, 2, 4 & 8 2 2, & 3 CS latency = 0 Write latency = 0 non buffered/non reg. Vcc tol +/- 10% 7.5 / 10.0 ns 5.4 / 6.0 ns not supported not supported 15/ 20 ns
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SPD-Table (cont'd):
Byte# Description SPD Entry Value Hex 8Mx64 -7.5 -8 0F 10 14 2D 15 08 15 08 14 2D 10 15 08 15 08 20 10 20 10 FF 12 E1 0A 68 E2 0B 69 15 08 15 08 15 08 15 08 20 10 20 10 16Mx64 -7.5 -8 0F 10 14 2D 14 2D
Minimum Row Active to Row Active delay 29 Minimum RAS to CAS delay 30 Minimum Ras pulse width 31 Module Bank Density (per bank) 32 SDRAM input setup time 33 SDRAM input hold time 34 SDRAM data input setup time 35 SDRAM data input hold time 36-61 Superset information 62 SPD Revision 63 Checksum for bytes 0 - 62 64- Manufactures's information (optional) 125 126 Frequency Specification 127 Details 128+ Unused storage locations
28
14 / 15 / 16 ns 15 / 20 ns 42 / 45 ns 64MB 1.5 / 2 ns 0.8 / 1 ns 1.5 / 2 ns 0.8 / 1 ns Revision 1.2
-7 0E 0F 2A
-7 0E 0F 2A
PC100 87
64 C7 FF
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HYS64V8200GDL/HYS64V16220GDL 144 pin SO-DIMM SDRAM Modules
Package Outlines 64 MByte SO-DIMM Module package (JEDEC MO-190) HYS64V8200GDL (144 pin, dual read-out, single in-line memory module)
67,6 63,6
0.13
0.15
3.8 max.
25.4 3.3 1
23.2
59 2.6 4.6
61
32.8
143
1 0.1
3.7 2 6 4
1.5 60 62 144
1.8
20
4
Detail of Contacts
Detail of Chamfer
0.6 0.8
0.2 -0.15
0.25
2.55
0.2 -0.15
L-DIM-144-10
Note: All tol eran ces accord ing to JEDEC stan dard
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HYS64V8200GDL/HYS64V16220GDL 144 pin SO-DIMM SDRAM Modules
128 MByte SO-DIMM Module package HYS64V16220GDL (144 pin, dual read-out, single in-line memory module)
67.6 63.6
0.13 0.15
3.8 max.
31.75 3.3 1
23.2 24.5
59
61 2.5
32.8
143
1 0.1
4.6 3.7 2 4 1.5 60 62 144 1.8
20
6 4 Detail of Contacts
Detail of Chamfer
0.25
0.6 0.8
L-DIM-144-9
0.2 -0.15
2.55
0.2 -0.15
Note : All toleran ces according to JEDEC stan dard
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HYS64V8200GDL/HYS64V16220GDL 144 pin SO-DIMM SDRAM Modules
Update Information:
5.6.99 29.9.99 3.12.99 17.1.2000 10.5.2000 19.7.2000 8.8.2000 25.9.2000 7.03.2001 5.09.2001
First and preliminary edition Checksum added PC133 timing changed according to INTELs PC133 specification HYS64V8200GDL-7.5/-8 added HYS64V162221GDL-7.5/-8 version with reduced height of 1060 mil = 29,92 mm (L-DIM-144-11) added CKE1 in two bank block diagram added 128Mbyte version HYS64V16221GDL removed (no plans for production) 8Mx64 module height on page 2 corrected -7 speed sort added SCR: Table for Absolute Maximum Ratings added
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